Hits:

DOI number:10.1049/iet-pel.2019.1242

Funded by:国家自然科学基金项目

First Author:Chen, Junlei

Co-author:吴翔,陈硕,谭国俊

Indexed by:Journal paper

Document Code:5b5bb294756ce67901756f5cf3ee044e

Volume:v 13,n 9,p1875-1884

ISSN No.:17554535

Translation or Not:no

Date of Publication:2020-07-24

Pre One:Synchronous reference frame single-phase phase-locked loop (PLL) algorithm based on half-cycle DFT Next One:All-Pass-Filter-Based PLL for Single-Phase Grid-Connected Converters Under Distorted Grid Conditions